CUDA: Hide latency of bias and gate-loading for fused mul_mat_vec_q
#16847
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This is realised by loading them into registers before computation of the dot-product, effectively batching them together with said dot-product. As a lot of threads are alive here, the warp scheduler has enough threads available to effectively hide the cost of additionally loading those two floats.
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Fixes #16815, benchmarks for affected devices (ampere cards with low memory bandwidth) can be found in the comments. Results on the RTX A4000:
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Pointed out [here](ggml-org#16847 (comment)) that only a single value is needed per target col per thread
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* CUDA: Remove unneded bias/gate dims in fused mmvq Pointed out [here](#16847 (comment)) that only a single value is needed per target col per thread * Apply suggestions from code review Co-authored-by: Johannes Gäßler <johannesg@5d6.de> * Fix "Error 991-D: extra braces are nonstandard" during compilation --------- Co-authored-by: Johannes Gäßler <johannesg@5d6.de>
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…is resolved revert ggml-org#16715 (+2 squashed commit) Squashed commit: [289af2ee2] Revert "Hide latency of bias and gate-loading (ggml-org#16847)" This reverts commit 8b11dee. [a3e5c1e95] Revert "CUDA: add unused vars to mmvf and mmvq (ggml-org#16807)" This reverts commit 463bbf2.
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This PR hides latency of bias and gate-loading for fused
mul_mat_vec_qkernel by loading them into registers before computation of the dot-product, effectively batching them together with said dot-product. As a lot of threads are alive in this part of the kernel still, the warp scheduler has enough threads available to effectively hide the cost of loading those two single floats.This gives 3-14% E2E speed-up for gpt-oss models (qwen3moe does not use bias and gate, and I am unaware of any other MoE model that uses bias and gate which I could run E2E perf tests on). The kernel themselves are up to 20% faster for gpt-oss.